• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a transistor including an impurity region and a gate on a semiconductor substrate, and forming a plug in electrical contact with the impurity region between the gate on the semiconductor substrate; Forming a protective film on the gate and the plug; forming a photoresist pattern on a portion corresponding to the predetermined plug on the protective film; and patterning the protective film using the photoresist pattern as a mask. Exposing the remaining plugs other than the plug; removing the exposed plug by using the photoresist pattern and the protective film as a mask; and removing the remaining protective film. Therefore, in the semiconductor device according to the present invention, the protective film is patterned by using a photoresist and the plug is etched by using the protective film as a mask. Etching process of the plug that requires is facilitated, and the thickness of the photoresist is reduced to reduce the exposure time and the dispersion of light energy, there is an advantage that can be applied to the ultra-high integrated circuit process requiring a fine pattern.
    公开号:KR19990040037A
    申请号:KR1019970060330
    申请日:1997-11-17
    公开日:1999-06-05
    发明作者:최정동
    申请人:구본준；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Manufacturing Method of Semiconductor Device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of effective etching during an etching process of a plug having a large aspect ratio and a mask and an etching selectivity not secured.
    1A to 1C are process diagrams illustrating a method of manufacturing a semiconductor device according to the prior art.
    In the related art, as shown in FIG. 1A, the field oxide film 13 is formed on the semiconductor substrate 11 by a conventional device isolation method such as a shallow trench isolation (STI) method or the like to define an active region. A gate oxide film 15 is formed on the semiconductor substrate 11 by thermal oxidation, and impurities are doped on the gate oxide film 15 by chemical vapor deposition (hereinafter, referred to as CVD). The polysilicon is deposited to form a first polysilicon layer, and silicon oxide or silicon nitride is deposited on the first polysilicon layer by CVD to form a cap insulation layer 19. Thereafter, the cap 17, the first polysilicon layer, and the gate insulating layer 15 are sequentially anisotropically etched by photolithography to define the gate 17. By using the cap insulating film 19 as a mask on the semiconductor substrate 11 on which the gate 17 is formed, impurities of different conductivity type from the semiconductor substrate 11 are implanted at low concentration to form a low concentration impurity region. A thick insulating material is deposited to cover the gate 17, and then etched back to form a side wall 21 on the side of the gate 17. The impurity region 23 used as a source / drain is formed by ion implanting impurities of a different conductivity type from the semiconductor substrate 11 using the cap insulating film 19 and the sidewall 21 as a mask. .
    Next, as shown in FIG. 1B, polycrystalline silicon doped with impurities is deposited between the gates 17 to cover the cap insulating layer 19 to form a second polysilicon layer, and the second polysilicon layer is etched back. A plug 25 is formed to planarize with the cap insulating film 19. In this case, the second polycrystalline silicon layer may be planarized to form the plug 25. The second insulating layer may be dry-etched or chemical mechanical polishing (hereinafter referred to as CMP). Flatten with (19). After the plug 25 is formed between the gates 17, a photoresist 27 is coated on the plug 25 and the cap insulating layer 19, and the photoresist 27 is exposed and developed to form a plug 25 between the gates 17. The pattern is formed such that the plug 25 is partially exposed.
    As shown in FIG. 1C, the plug 25 between the partially exposed gates 17 is used as the mask using the remaining photoresist 27 as a mask to which chlorine (Cl), fluorine (F), or the like is added. Dry etch and remove the remaining photoresist (27). The plug 25 remaining due to the photoresist 27, which is a mask, is used as a storage node plug of a capacitor or a plug of a bit line.
    As described above, in the related art, after forming a transistor including an impurity region and a gate, a plug is formed between the gates, and the plug is etched using a photoresist as a mask to selectively remove the plug.
    However, in order for the aspect ratio of the plugs between the gates to be 4 or more, and in order to completely remove the plugs of the open portions, an etching target may be 2 to 3 times the longitudinal length of the plugs to be etched. It should be more than doubled. For this purpose, the etching selectivity between the photoresist and the plug being etched must be at least 1: 5 or the thickness of the photoresist must be at least about four times the longitudinal length of the plug so that the etching target can be used as a mask sufficiently. Only exposed plugs can be selectively etched without loss of plugs. However, as the etching gas containing chlorine or fluorine, it is difficult to obtain an etching selectivity of photoresist, polycrystalline silicon, and 1: 5, and when a photoresist, which is another method, is formed thick, a lot of time is lost during the exposure process. there was.
    Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which facilitates etching of a plug whose aspect ratio is large and thus the etching selectivity is not secured.
    In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a transistor including an impurity region and a gate on a semiconductor substrate, and electrically contacting the impurity region between the gate on the semiconductor substrate. Forming a plug to be formed; forming a protective film on the gate and the plug; forming a photoresist pattern on a portion corresponding to the predetermined plug on the protective film; and using the photoresist pattern as a mask. Patterning the protective film to expose the remaining plugs except for the predetermined plug; removing the exposed plug by using the photoresist pattern and the protective film as a mask; and removing the remaining protective film. .
    1A to 1C are process drawings showing a method for manufacturing a semiconductor device according to the prior art.
    2A to 2D are process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
    <Brief description of symbols for the main parts of the drawings>
    31: semiconductor substrate 33: field oxide film
    37 gate 39 cap insulating film
    45: plug 47: protective film
    Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
    2A to 2D are process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
    As shown in Fig. 2A, the field oxide film 33 is formed on the semiconductor substrate 31 by a conventional device isolation method such as the STI method to define the active region. A gate oxide film 35 is formed on the semiconductor substrate 31 by a thermal oxidation method, and polycrystalline silicon doped with impurities is deposited on the gate oxide film 35 by CVD to form a first polysilicon layer. Then, silicon oxide or silicon nitride is deposited on the first polysilicon layer by CVD to form a cap insulating film 39. Thereafter, the cap insulation layer 39, the first polysilicon layer, and the gate insulation layer 35 are sequentially anisotropically etched by photolithography to define the gate 37. By using the cap insulating film 39 as a mask on the semiconductor substrate 31 on which the gate 37 is formed, impurities having different conductivity types from that of the semiconductor substrate 31 are ion implanted at low concentration to form a low concentration impurity region. A thick insulating material is deposited to cover the gate 37 and then etched back to form sidewalls 41 on the side surfaces of the gate 37. The impurity region 43 used as a source / drain is formed by ion implanting impurities of a different conductivity type from the semiconductor substrate 31 using the cap insulating layer 39 and the sidewalls 41 as a mask. .
    Next, as shown in FIG. 2B, a polysilicon doped with an impurity is deposited between the gates 37 to cover the cap insulation layer 39 to form a second polysilicon layer and then etch back to form a second polysilicon layer. A plug 45 is formed to planarize. In the method of forming the plug 45 by planarizing the second polysilicon, the second polysilicon layer may be dry etched or polished by a CMP method to be flat with the cap insulation layer 39. Silicon oxide or silicon nitride is deposited on the flat plug 45 and the cap insulating film 39 by CVD to form a protective film 47. After the photoresist 49 is applied on the passivation layer 47, the photoresist 49 is exposed and developed to form a pattern to partially expose the passivation layer 47 on the plug 45 between the gates 37.
    As shown in FIG. 2C, the partially exposed protective film 47 is patterned using the remaining photoresist 49 on the protective film 47 as a mask. The passivation layer 47 has a high etching selectivity with the polysilicon, it is possible to control the etching selectivity even with a low thickness of about 500Å.
    Then, as shown in FIG. 2D, O 2 is added to Cl 2 / HBr or the plug 45 between the exposed gate 37 using the remaining photoresist and protective layers 49 and 47 as a mask or SF 6 The photoresist and the protective films 49 and 47 which are dry etched and remain by using a gas to which N 2 is added to are removed by the CMP method. When the protective film 47 is removed by the CMP method, the loss amount of the cap insulating film 39 is controlled to be less than 300 GPa so that the gate 37 is not exposed. The remaining plug 45 due to the photoresist and passivation layers 49 and 47 is used as a storage electrode plug of a capacitor and a plug of a bit line.
    As described above, in the present invention, after the transistor including the impurity region and the gate is formed, a plug is formed between the gates and a protective film is formed to selectively remove the plug. The protective film was patterned using a photoresist as a mask, and the plug of the exposed portion was dry etched using the remaining photoresist and the patterned protective film.
    Therefore, in the semiconductor device according to the present invention, the protective film is patterned by using a photoresist and the plug is etched by using the protective film as a mask. Etching process of the plug that requires is facilitated, and the thickness of the photoresist is reduced to reduce the exposure time and the dispersion of light energy, there is an advantage that can be applied to the ultra-high integrated circuit process requiring a fine pattern.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] Forming a transistor including an impurity region and a gate on the semiconductor substrate;
    Forming a plug in electrical contact with the impurity region between the gates on the semiconductor substrate;
    Forming a protective film on the gate and the plug;
    Forming a photoresist pattern on a portion of the protective film that corresponds to the predetermined plug;
    Patterning the passivation layer using the photoresist pattern as a mask to expose the remaining plugs except for the predetermined plug;
    Removing the exposed plug by using the photoresist pattern and the protective film as a mask;
    And a step of removing the remaining protective film.
    [2" claim-type="Currently amended] The method of claim 1, wherein the passivation layer is formed of silicon oxide or silicon nitride.
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    同族专利:
    公开号 | 公开日
    KR100255005B1|2000-05-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-11-17|Application filed by 구본준, 엘지반도체 주식회사
    1997-11-17|Priority to KR1019970060330A
    1999-06-05|Publication of KR19990040037A
    2000-05-01|Application granted
    2000-05-01|Publication of KR100255005B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970060330A|KR100255005B1|1997-11-17|1997-11-17|Manufacturing method of semiconductor device|
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